3D-IC Partitioning
The experiments are limited to the Open3DBench memory-on-logic scenario and its eight designs. 3D integrated circuits use vertical die stacking and dense interconnects to improve integration density and potentially shorten important connec…
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The experiments are limited to the Open3DBench memory-on-logic scenario and its eight designs. 3D integrated circuits use vertical die stacking and dense interconnects to improve integration density and potentially shorten important connections. Partitioning gate-level netlists across tiers is difficult because final PPA is unknown before backend implementation. The studied partitioning problem assigns memory blocks across tiers while keeping logic cells on the bottom tier.